1. Field of the Invention
The present invention relates generally to electronics and computers.
2. Description of the Background Art
Interconnects of various kinds pose a significant failure mechanism for computer servers. A typical failure mode for interconnects is for a loss of continuity (an open circuit) to occur due to mechanical stress, vibrations, shock, contaminant build-up, poor assembly, and other reasons. This loss of continuity can cause system failures, which are difficult and costly to debug. In addition, no simple, efficient method currently exists to determine the seating (i.e., connection integrity) of an interconnect prior to system assembly and test.
One prior solution to determine the status of an interconnect is to perform continuity checks of an interconnect by hand with an ohm (resistance) meter. This technique is inefficient, time consuming, requires additional test hardware, and is difficult to accurately and quickly perform.
Another prior solution is to perform automatic testing using a bed-of-nails test fixture. Such testing is practical for printed-circuit assemblies having only one layer and with test pads built into the boards. Probes from the bed-of-nails fixture would make contact with the test pads, and tests could be run to locate interconnect defects, such as opens or shorts. However, this technique has become impractical as electronic systems became smaller, wires on the board became denser, devices became placed on both sides of a board, and so on. In addition, bed of nails testers typically test a single non-mated board, not an interconnection between a mated pair of boards. Also bed of nails testing requires a large test fixture and is typically only done for first board build, or if a board is removed from the system and sent back for debug.
Another prior solution is to run boundary-scan (SCAN) testing. This type of testing requires special software and training and typically cannot be performed until the system is assembled and powered on.
The above-described problems and disadvantages may be overcome by utilizing embodiments of the present invention.